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LT3688 1 3688f typical application features applications description dual 800ma step-down switching regulator with power-on reset and watchdog timer the lt ? 3688 is an adjustable frequency (350khz to 2.2mhz) dual monolithic step-down switching regulator with two power-on reset timers and a watchdog timer. the regulator operates off inputs up to 36v. low ripple burst mode ? operation maintains high ef? ciency at low output current while keeping output ripple below 25mv in a typical application, with input quiescent current of just 115a. shutdown circuitry reduces input supply current to less than 1a while en/uvlo is pulled low. the reset and watchdog timeout periods are both adjust- able using external capacitors. tight accuracy speci? ca- tions and glitch immunity ensure reliable reset operation without false triggering. the open collector rst pins will pull down if the monitored output voltage drops 10% below the programmed value. the LT3688 watchdog timer monitors for watchdog falling edges grouped too close together or too far apart. the LT3688 is available in 24-pin tssop and 4mm 4mm qfn packages, each with an exposed pad for low thermal resistance. 5v and 3.3v regulator with power-on reset and watchdog timers n wide input range: operation from 3.8v to 36v n low ripple (<25mv p-p ) burst mode operation: i q = 115a at 12v in to 3.3v and 5v n programmable, defeatable window watchdog timer n two independently programmable power-on-reset timers n synchronizable, adjustable 350khz-2.2mhz switching frequency n two 800ma output switching regulators with internal power switches n programmable input undervoltage lockout with hysteresis n thermally enhanced 24-pin tssop and 4mm 4mm qfn packages n automotive electronic control units n industrial power supplies n high-reliability processor systems en/uvlo v in LT3688 gnd bias bst1 0.22f 4.7f v out1 5v 800ma v in 6v to 36v 22f 22pf 18h 12h 523k 100k 316k 100k 1nf 1nf p 0.22f sw1 da1 bst2 sw2 da2 fb1 run/ss1 wdi wdo rst1 rst2 i/o i/o reset fb2 run/ss2 c wdt c por1 c por2 rt sync 22f 1nf 3688 ta01a 4.7nf 4.7nf 110k f sw = 500khz v out2 3.3v 800ma 22pf ef? ciency 3688 ta01b 0.0001 1 0.001 0.01 0.1 load current (a) efficiency (%) 60 70 80 50 30 40 90 power loss (mw) 10.0 100.0 1000.0 1.0 0.01 0.1 10000.0 v in = 12v v out = 3.3v l = 4.7h f = 800khz l , lt, ltc, ltm, burst mode, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. www.datasheet.co.kr datasheet pdf - http://www..net/
LT3688 2 3688f absolute maximum ratings v in , en/uvlo, config voltage (note 2) ...................36v bst voltage ..............................................................55v bst above sw voltage .............................................30v bias voltage .............................................................30v wde, wdi, rst, wdo voltage ...................................6v fb, rt , sync, run/ss voltage ..................................6v c wdt , c por voltage ....................................................3v 1 2 3 4 5 6 7 8 9 10 11 12 top view fe package 24-lead plastic tssop 24 23 22 21 20 19 18 17 16 15 14 13 fb1 run/ss1 bst1 sw1 da1 v in config da2 sw2 bst2 run/ss2 fb2 en/uvlo sync rt c wdt c por1 bias c por2 wdi wde wdo rst1 rst2 25 gnd ja = 38c/w exposed pad (pin 25) is gnd, must be electrically connected to pcb 24 23 22 21 20 19 7 8 9 top view uf package 24-lead (4mm 4mm) plastic qfn 10 11 12 6 5 4 3 2 1 13 14 15 16 17 18 rt sync en/uvlo fb1 run/ss1 bst1 wdo rst1 rst2 fb2 run/ss2 bst2 c wdt c por1 bias c por2 wdi wde sw1 da1 v in config da2 sw2 25 gnd ja = 37c/w exposed pad (pin 25) is gnd, must be electrically connected to pcb pin configuration order information lead free finish tape and reel part marking* package description temperature range LT3688efe#pbf LT3688efe#trpbf LT3688fe 24-lead plastic tssop C40c to 125c LT3688ife#pbf LT3688ife#trpbf LT3688fe 24-lead plastic tssop C40c to 125c LT3688hfe#pbf LT3688hfe#trpbf LT3688fe 24-lead plastic tssop C40c to 150c LT3688euf#pbf LT3688euf#trpbf 3688 24-lead (4mm 4mm) plastic qfn C40c to 125c LT3688iuf#pbf LT3688iuf#trpbf 3688 24-lead (4mm 4mm) plastic qfn C40c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www .linear.com/tapeandreel/ (note 1) operating junction temperature range (note 3) LT3688e, LT3688i ..............................C40c to 125c LT3688h ............................................C40c to 150c maximum junction temperature LT3688e, LT3688i ............................................. 125c LT3688h ........................................................... 150c storage temperature range ...................C 65c to 150c lead temperature (soldering, 10 sec) fe package ....................................................... 300c www.datasheet.co.kr datasheet pdf - http://www..net/
LT3688 3 3688f the l denotes the speci? cations which apply over the full operating junction temperature range, otherwise speci? cations are at t a = 25c. v in = 12v, unless otherwise noted. (note 3) electrical characteristics symbol parameter conditions min typ max units v in undervoltage lockout l 3 3.5 3.8 v quiescent current from v in v en/uvlo = 0.3v v bias = 5v, not switching v bias = 0v, not switching l 0.01 65 235 1 105 310 a a a quiescent current from bias v en/uvlo = 0.3v v bias = 5v, not switching v bias = 0v, not switching l 0.01 155 C5 1 200 C20 a a a fb voltage l 0.790 0.784 0.800 0.810 0.814 v v fb pin bias current v fb = 0.800v l C3 C50 na fb voltage line regulation 5v < v in < 36v 0.002 %/v switching frequency r t = 20k, v bst = 12v r t = 110k, v bst = 12v l l 1.85 460 2.1 500 2.35 540 mhz khz minimum off-time (note 4) v bst = 12v l 115 180 ns switch current limit (note 5) dc = 15% l 1.2 1.7 2.2 a switch v cesat i sw = 0.8a 280 mv switch leakage current (note 8) C0.01 C1 a da current limit l 0.9 1.2 1.6 a boost schottky reverse leakage v bias = 0v 0.01 2 a minimum bst voltage above sw 2.15 2.5 v bst pin current i sw = 0.8a 15 25 ma en/uvlo threshold voltage l 1.15 1.25 1.35 v en/uvlo input current v en/uvlo = 1.35v v en/uvlo = 1.15v 2.5 0.3 46 a a threshold current hysteresis 2.5 3.7 5.5 a run/ss pin current v run/ss = 0v C1.4 C2.8 C4 a run/ss switching threshold 0.15 0.8 1 v sync threshold voltage 0.4 0.8 1.3 v v uv reset threshold % of fb voltage, v fb falling l 88 90 92 % t rst reset timeout period c por = 4700pf l 21.2 23.5 25.8 ms t wdu watchdog window upper boundary c wdt = 1000pf l 18 20 22 ms t wdl watchdog window lower boundary c wdt = 1000pf l 0.8 1.25 1.6 ms t wdto watchdog timeout period c wdt = 1000pf 2.5 ms rst output voltage low i sink = 2.5ma, v fb = 0.6v i sink = 100a, v fb = 0.6v l l 0.2 0.01 0.4 0.3 v v t uv uv detect to rst asserted v fb set to 0.680v l 41030 s wdi input threshold l 0.4 0.95 1.3 v wdi input pull-up current C2 a wdi input pulse width l 300 ns wde threshold voltage l 0.4 0.65 1 v wde input pull-down current v wde = 1.2v 3.5 a wdo output voltage low i sink = 2.5ma i sink = 100a l l 0.2 0.01 0.4 0.3 v v www.datasheet.co.kr datasheet pdf - http://www..net/
LT3688 4 3688f the l denotes the speci? cations which apply over the full operating junction temperature range, otherwise speci? cations are at t a = 25c. v in = 12v, unless otherwise noted. (note 3) symbol parameter conditions min typ max units rst pull-up current (note 6) C1.5 C2.5 a wdo pull-up current (note 6) C1.5 C2.5 a config low level input voltage l 0.2 v config high level input voltage l 1.4 v config pin voltage when open 0.64 v maximum config input current in open state l 1 a config pin bias current v config = 0v, v in l 20 a electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: absolute maximum voltage at the v in , config and en/uvlo pins is 36v for continuous operation. note 3: the LT3688 is tested under pulsed load conditions such that t j = t a . the LT3688e is guaranteed to meet performance speci? cations from 0c to 125c junction temperature. speci? cations over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LT3688i is guaranteed over the full C40c to 125c operating junction temperature range. the LT3688h is guaranteed over the full C40c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes. operating lifetime is derated at junction temperatures greater than 125c. the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (pd, in watts) according to the formula: t j = t a + (pd ja ), where ja (in c/w) is the package thermal impedance. note 4: the LT3688 contains circuitry that extends the maximum duty cycle if the bst voltage is 2v greater than the sw voltage. see the applications information section for more details. note 5: current limit is guaranteed by design and/or correlation to static test. slope compensation reduces current limit at higher duty cycles. note 6: the outputs of rst and wdo have a weak pull-up to v bias of typically 2.5a. however, external pull-up resistors may be used when faster rise times are required or for v oh higher than v bias . note 7: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed the maximum operating junction temperature when over-temperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability. note 8: all currents into pins are positive; all voltages are referenced to gnd unless otherwise speci? ed. typical performance characteristics ef? ciency, v out = 5v ef? ciency, v out = 3.3v ef? ciency, v out = 1.8v t a = 25c unless otherwise noted. load current (a) 0 0.2 0.4 0.6 0.8 1 65 efficiency (%) 85 90 80 70 75 95 3688 g01 f sw = 1mhz v in = 12v load current (a) 0 0.2 0.4 0.6 0.8 1 60 efficiency (%) 80 85 75 65 70 90 3688 g02 f sw = 1mhz v in = 12v load current (a) 0 0.2 0.4 0.6 0.8 1 55 efficiency (%) 75 80 70 60 65 85 3688 g03 f sw = 500khz v in = 12v www.datasheet.co.kr datasheet pdf - http://www..net/
LT3688 5 3688f typical performance characteristics no-load supply current (input) no-load supply current (temperature) maximum load current (5v) maximum load current (3.3v) switch current limit vs duty cycle switch current limit vs temperature t a = 25c unless otherwise noted. v in (v) 0 10203040 0 supply current (a) 120 140 100 40 60 20 80 160 3688 g04 v out1 = 5v v out2 = 3.3v input voltage (v) 010203040 0 load current (a) 1.5 0.5 1 2 3688 g06 l = 15h l = 10h f sw = 1mhz input voltage (v) f sw = 1mhz 0 10203040 0 load current (a) 1.5 0.5 1 2 3688 g07 l = 15h l = 10h duty cycle (%) 0 20406080100 0 current limit (a) 1.4 0.2 0.4 0.6 1 1.2 1.6 0.8 1.8 3688 g08 typical min temperature (c) C50 C25 0 50 75 25 100 125 150 0 current limit (a) 0.5 1.0 1.5 2.0 3688 g09 dc = 15% switch voltage drop bst pin current feedback voltage switch current (ma) 0 200 400 800 600 1000 0 switch voltage (mv) 50 100 150 250 300 200 350 3688 g10 switch current (ma) 0 200 400 800 600 1000 0 bst pin current (ma) 5 15 20 10 25 3688 g11 temperature (c) C50 C20 25 50 0 100 125 75 150 0.790 feedback voltage (v) 0.795 0.805 0.800 0.810 3688 g12 temperature (c) C50 C25 0 25 50 75 100 125 150 0 supply current (a) 2500 1000 1500 500 2000 3000 3688 g05 catch diode: b140hb v in = 12v v out1 = 5v v out2 = 3.3v increased supply current due to catch diode leakage at high temperature www.datasheet.co.kr datasheet pdf - http://www..net/
LT3688 6 3688f typical performance characteristics switching frequency vs r t switching frequency vs temperature minimum switch on-time en/uvlo pin current en/uvlo pin threshold boost diode forward voltage switching waveforms, burst mode operation switching waveforms, transition from burst mode to full frequency switching waveforms, full frequency continuous operation t a = 25c unless otherwise noted. temperature (c) r t = 49.9k C50 C25 25 50 0 100 125 75 150 0.0 switching frequency (mhz) 0.2 0.8 0.6 0.4 1.2 1.0 3688 g14 temperature (c) i sw = 700ma C50 C20 25 50 0 100 125 75 150 0 minimum on time (ns) 50 150 100 200 3688 g16 pin voltage (v) 0 5 15 20 10 30 35 25 40 0 pin current (a) 5 15 20 10 25 3688 g17 temperature (c) threshold falling C50 C25 25 50 0 100 125 75 150 1.00 en/uvlo pin threshold (v) 1.10 1.30 1.40 1.20 1.50 3688 g18 current (ma) 0 1020304050 0 forward voltage (mv) 100 500 600 700 800 200 300 400 900 3688 g19 i l 0.2a/div v in = 12v; front page application i load = 40ma v sw 5v/div v out 10mv/div 5s/div 3688 g21 i l 0.2a/div v in = 12v; front page application i load = 160ma v sw 5v/div v out 10mv/div 5s/div 3688 g22 r t (k) 0 100 50 150 200 0 switching frequency (mhz) 0.5 1.5 2.0 1.0 2.5 3688 g13 i l 0.2a/div v in = 12v; front page application i load = 7ma v sw 5v/div v out 10mv/div 5s/div 3688 g20 www.datasheet.co.kr datasheet pdf - http://www..net/
LT3688 7 3688f typical performance characteristics power-on reset threshold vs temperature typical transient duration vs comparator overdrive watchdog window mode period vs temperature reset timeout period (t rst ) vs temperature t a = 25c unless otherwise noted. temperature (c) C50 C25 0 25 50 75 100 125 150 0.710 v uv (v) 0.725 0.715 0.720 0.730 3688 g23 overdrive voltage (% of v uv ) 0.1 1 10 100 0 reset delay (s) 600 100 200 300 400 500 700 3688 g24 temperature (c) c wdt = 1000pf C50 C25 0 25 50 75 100 125 150 0 t wdu (ms) 5 10 15 20 25 3688 g26 temperature (c) c por = 4700pf C50 C25 0 25 50 75 100 125 150 0 t rst (ms) 5 10 15 20 25 30 3688 g27 reset timeout period (t rst ) vs capacitance c por (nf) 0.001 0.1 10 1000 100000 0.01 t rst (ms) 0.1 10 100 1000 10000 1 100000 3688 g28 watchdog window lower boundary (t wdl ) vs capacitance watchdog window upper boundary (t wdu ) vs capacitance c wdt (nf) 0.001 0.1 10 1000 100000 0.01 t wdl (ms) 0.1 10 100 1000 10000 1 100000 3688 g29 c wdt (nf) 0.001 0.1 10 1000 100000 0.1 t wdu (ms) 1 10 100 1000 10000 100000 3688 g30 www.datasheet.co.kr datasheet pdf - http://www..net/
LT3688 8 3688f rt (pin 1/pin 22): the rt pin is used to set the internal oscillator frequency. tie a resistor from rt to gnd to set the switching frequency. sync (pin 2/pin 23): drive the sync pin with a logic- level signal with positive and negative pulse widths of at least 150ns. do not ? oat this pin. tie to gnd if the sync feature is not used. en/uvlo (pin 3/pin 24): the en/uvlo pin is used to put the LT3688 in shutdown mode. pull the pin below 0.3v to shut down the LT3688. the 1.25v threshold can function as an accurate undervoltage lockout (uvlo), preventing the regulator from operating until the input voltage has reached the programmed level. fb1, fb2 (pins 4, 15/pins 1, 12): the LT3688 regulates the feedback pins to 0.800v. connect the feedback resistor divider taps to this pin. run/ss1, run/ss2 (pins 5, 14/pins 2, 11): place a capacitor from run/ss to gnd to program the soft start period. use a 1000pf or larger capacitor at these pins. to ensure the ss capacitors are discharged, internal circuitry pulls the run/ss pins low and disables switching during startup before initiating the soft-start sequence. once the run/ss pins fall below 0.2v, the pull down turns off, the ss capacitors start charging again, and switching is enabled. do not drive these pins directly. use an open drain or collector to pull them low, if necessary. bst1, bst2 (pins 6, 13/pins 3, 10): the bst pins are used to provide drive voltage, higher than the input volt- age, to the internal npn power switches. sw1, sw2 (pins 7, 12/pins 4, 9): the sw pins are the outputs of the internal power switches. connect these pins to the inductors, catch diodes and boost capacitors. da1, da2 (pins 8, 11/pins 5, 8): tie the da pin to the anode of the external catch schottky diode. if the da pin current exceeds 1.2a, which could occur in an overload or short-circuit condition, switching is disabled until the da pin current falls below 1.2a. v in (pin 9/pin 6): the v in pin supplies current to the LT3688s internal circuitry and to the internal power switches and must be locally bypassed. pin functions config (pin 10/pin 7): the config pin programs the start-up sequence of the two voltage regulators and the behavior of the power-on reset and watchdog timers. to select one of three con? guration options, tie the config pin to v in , tie the config pin to gnd or leave the config pin ? oating. with the config pin tied to v in , each reset output depends on its respective fb pin. channel 2 only starts when fb1 rises above 0.72v, and the watchdog timer only starts when both rst pins go high. with the config pin tied to gnd, both rst pins pull low until both fb pins rise above 0.72v and the por timer programmed by c por1 expires. again, channel 2 only starts when fb1 rises above 0.72v, and the watchdog timer only starts when both rst pins go high. tie c por2 to gnd if the config pin is tied low. with the config pin ? oating, both channels start coincidentally, each reset output depends on its respective fb pin, and the watchdog timer starts when rst1 goes high. rst1, rst2 (pins 17, 16/pins 14, 13): the rst pins are active low, open-drain logic outputs with a weak pull-up to bias. after v fb rises above 0.72v, the reset remains asserted for the period set by the capacitor on the c por pin. tie the rst pins to bias with a 100k resistor for a stronger pull-up. wdo (pin 18/pin 15): wdo will go low if the micropro- cessor fails to drive the wdi pin of the LT3688 with the appropriate signal. tie the wdo pin to bias with a 100k resistor for a stronger pull-up. keep capacitive loading on this pin below 1000pf. wde (pin 19/pin 16): the watchdog timer enable pin disables the watchdog timer if the wde voltage exceeds 1v. float this pin or tie to ground for normal operation. wdi (pin 20/pin 17): the watchdog timer input pin receives the watchdog signal from the microprocessor. if two or more negative edges occur on wdi before the programmed fast timer period or no negative edge occurs within the slow timer period, the part will pulse wdo low with a pulse width of 1/8th of the slow timer period. drive the wdi pin with a pulse width of at least 300ns. bias (pin 22/pin 19): the bias pin supplies current to the internal circuitry when bias is above 3v, helping reduce input quiescent current. the internal schottky diodes are connected from bias to bst, providing the charging path for the boost capacitors. (qfn/tssop) www.datasheet.co.kr datasheet pdf - http://www..net/
LT3688 9 3688f pin functions (qfn/tssop) c por1 , c por2 (pins 23, 21/pins 20, 18): place a capacitor between this pin and ground to set the power-on-reset timeout period. c wdt (pin 24/pin 21): place a capacitor between this pin and ground to set the fast and slow watchdog timer periods. exposed pad (pin 25/pin 25): ground. tie the exposed pad directly to the ground plane. the exposed pad metal of the package provides both electrical contact to ground and good thermal contact to the printed circuit board. the device must be soldered to the circuit board for proper operation. block diagram + C + C + C + bst2 sw2 da2 r sen2 disable q s r rt r t slave oscillator master oscillator internal 0.8v ref error amp slope comp switch latch burst mode operation detect adjustable reset pulse generator v c clamp c5 c c v in 3.4v r c v c c4 out2 l2 fb2 run/ss2 c por2 2.5a 22a 3688 bd01 rst2 bias out1 sync v in v in en/uvlo on off + C + C + C + bst1 sw1 da1 r sen1 q s r slave oscillator configuration logic watchdog timer transition detect slope comp switch latch burst mode operation detect adjustable reset pulse generator v c clamp out1 fb1 r2 r1 c2 c3 l1 run/ss1 c por1 2.5a 2a 22a 22a rst1 c wdt wde wdi wdo config gnd three-state decode + C + C 80mv c1 www.datasheet.co.kr datasheet pdf - http://www..net/
LT3688 10 3688f operation the LT3688 is a constant-frequency, current mode step- down regulator with two reset timers and a watchdog timer that perform microprocessor supervisory functions. operation can be best understood by referring to the block diagram. keeping the en/uvlo pin at ground completely shuts off the part drawing minimal current from the v in source. to turn on the internal bandgap and the rest of the logic circuitry, raise the en/uvlo pin above the accurate threshold of 1.25v. also, v in needs to be higher than 3.5v for the part to start switching. switching regulator operation an oscillator, with frequency set by r t , enables an rs ? ip ? op, turning on the internal power switch. an ampli? er and comparator monitor the current ? owing between the v in and sw pins, turning the switch off when this cur- rent reaches a level determined by the voltage at v c . an error ampli? er measures the output voltage through an external resistor divider tied to the fb pin and servos the v c voltage. if the error ampli? ers output increases, more current is delivered to the output; if it decreases, less current is delivered. an active clamp on the v c voltage provides current limit. the v c voltage is also controlled by the internal soft-start circuit during start-up or after a fault condition takes place. an internal regulator provides power to the control cir- cuitry. the internal regulator normally draws current from the v in pin, but if the bias pin is connected to an external voltage higher than 3v, bias current will be drawn from the external source (typically the regulated output voltage). this improves ef? ciency. the bias pin also provides a current path to the internal boost diode that charges up the boost capacitor. the switch driver operates either from the v in or from the bst pin. an external capacitor is used to generate a voltage at the bst pin that is higher than the v in supply. this allows the driver to fully saturate the internal npn power switch for ef? cient operation. to further optimize ef? ciency, the LT3688 automatically switches to burst mode operation in light load situations. between bursts, all circuitry associated with controlling the output switch is shut down, reducing the input supply current to 115a in a typical application. a comparator monitors the current ? owing through the catch diode via the da pin. this comparator delays switch- ing if the diode current goes higher than 1.2a (typical) during a fault condition such as a shorted output with high input voltage. switching will only resume once the diode current has fallen below the 1.2a limit. this way the da comparator regulates the valley current of the inductor to 1.2a during short circuit. this will ensure that the part will survive a short-circuit event. power-on reset and watchdog timer operation the LT3688 has two power-on reset comparators that monitor the regulated output voltages. if v out is 10% below the regulation value, the rst pin is pulled low. once the output voltage crosses over 90% of the regulation value, a reset timer is started and rst is released after the programmed reset delay time. the reset delay is programmable through the c por pin. the watchdog typically monitors a microprocessors activity. the watchdog can be enabled or disabled by ap- plying a logic signal to the wde pin. the watchdog timer requires successive negative edges on the wdi pin to come within a programmed time window to keep wdo from going low. if the time between the two negative wdi edges is too short or too long, then the wdo pin will be pulled low. when the wdo pin goes low, it stays low for a time period equivalent to 1/8th of the watchdog window upper boundary. the wdo pin will go high again once the timer expires or if the rst pin goes low. the watchdog window upper and lower boundaries can be set through the c wdt pin. www.datasheet.co.kr datasheet pdf - http://www..net/
LT3688 11 3688f timing diagrams 3686 td01 t wdu t < t wdl t wdto t wdto wdi wdo t rst t uv v out v uv rst power-on reset timing watchdog timing www.datasheet.co.kr datasheet pdf - http://www..net/
LT3688 12 3688f timing diagrams t wdu t rst2 t rst1 v out1 v out2 v uv v uv rst1 rst2 wdo startup timing (v config = high) wdi t wdu t rst2 t rst1 v out1 v out2 v uv v uv rst1 rst2 wdo startup timing (v config = open) wdi t wdu t rst1 v out1 rst1 v uv v uv v out2 rst2 wdo startup timing (v config = low) wdi t rst1 = programmed reset period (c por1 ) t rst2 = programmed reset period (c por2 ) t wdu = watchdog window upper boundry v uv = reset threshold 3688 td www.datasheet.co.kr datasheet pdf - http://www..net/
LT3688 13 3688f applications information setting the output voltage the output voltage is programmed with a resistor divider between the output and the fb pin. choose the 1% resistors according to: r1 = r2 v out 0.8v C1 ? ? ? ? ? ? for reference designators, refer to the block diagram. setting the switching frequency the LT3688 uses a constant-frequency pwm architecture that can be programmed to switch from 350 khz to 2.2 mhz by using a resistor tied from the rt pin to ground. table 1 shows the r t values for various switching frequencies table 1. switching frequency vs r t switching frequency (mhz) r t (k) 0.35 165 0.5 110 0.6 88.7 0.7 75 0.8 64.9 0.9 56.2 1 49.9 1.2 40.2 1.4 33.2 1.6 27.4 1.8 23.2 2.1 20 2.3 17.4 operating frequency tradeoffs selection of the operating frequency is a tradeoff between ef? ciency, component size and maximum input voltage. the advantage of high frequency operation is that smaller inductor and capacitor values may be used. the disadvantages are lower ef? ciency, and narrower input voltage range at constant-frequency. the highest constant- switching frequency (f sw(max) ) for a given application can be calculated as follows: f sw(max) = v out + v f t on(min) v in + v f Cv sw () where v in is the typical input voltage, v out is the output voltage, v f is the catch diode drop (~0.5v) and v sw is the internal switch drop (~0.3v at maximum load). if the LT3688 is programmed to operate at a frequency higher than f sw(max) for a given input voltage, the LT3688 enters pulse skip mode, where it skips switching cycles to maintain regulation. at frequencies higher than f sw(max) , the LT3688 no longer operates with constant frequency. the LT3688 enters pulse skip mode at frequencies higher than f sw(max) because of the limitation on the LT3688s minimum on time of 140ns (180ns for t j > 125c). as the switching frequency is increased above f sw(max) , the part is required to switch for shorter periods to maintain the same duty cycle. delays associated with turning off the power switch dictate the minimum on-time of the part. when the required on-time decreases below the minimum on-time of 140ns, the switch pulse width remains ? xed at 140ns (instead of becoming narrower) to accommodate the same duty cycle require- ment. the inductor current ramps up to a value exceeding the load current and the output ripple increases. the part then remains off until the output voltage dips below the programmed value before it begins switching again. maximum operating voltage range the maximum input voltage for LT3688 applications depends on switching frequency, the absolute maximum ratings of the v in and bst pins, and by the minimum duty cycle (dc min ). the LT3688 can operate from input voltages up to 36v. dc min = t on(min) ? f sw where t on(min) is equal to 140ns and f sw is the switching frequency. running at a lower switching frequency allows a lower minimum duty cycle. the maximum input voltage before pulse-skipping occurs depends on the output volt- age and the minimum duty cycle: v in(ps) = v out + v f dc min Cv f + v sw example: f = 2.1mhz, v out = 3.3v dc min = 140ns ? 2.1mhz = 0.294 v in(ps) = 3.3v + 0.5v 0.294 C 0.5v + 0.3v = 12.7v www.datasheet.co.kr datasheet pdf - http://www..net/
LT3688 14 3688f applications information the LT3688 will regulate the output voltage at input volt- ages greater than v in(ps) . for example, an application with an output voltage of 3.3v and switching frequency of 2.1mhz has a v in(ps) of 12.7v, as shown in figure 1. figure 2 shows operation at 27v. output ripple and peak inductor current have signi? cantly increased. a saturating inductor may further reduce performance. in pulse skip mode, the LT3688 skips switching pulses to maintain output regulation. the LT3688 will also skip pulses at very low load currents. v in(ps) vs load current is plotted in the typical performance section. v out 50mv/div (ac) i l 500ma/div 2s/div 3688 f01 figure 1. operation below pulse-skipping voltage. v out = 3.3v and f sw = 2.1mhz v out 50mv/div (ac) i l 500ma/div 2s/div 3688 f02 figure 2. operation above v in(ps) . v in = 27v, v out = 3.3v and f sw = 2.1mhz. output ripple and peak inductor current increase minimum operating voltage range the minimum input voltage is determined either by the LT3688s minimum operating voltage of ~3.6v or by its maximum duty cycle. the duty cycle is the fraction of time that the internal switch is on and is determined by the input and output voltages: dc = v out + v f v in Cv sw + v f unlike many ? xed frequency regulators, the LT3688 can extend its duty cycle by remaining on for multiple cycles. the LT3688 will not switch off at the end of each clock cycle if there is suf? cient voltage across the boost capacitor (c3 in the block diagram). eventually, the voltage on the boost capacitor falls and requires refreshing. circuitry detects this condition and forces the switch to turn off, allowing the inductor current to charge up the boost capacitor. this places a limitation on the maximum duty cycle as follows: dc max = 90% this leads to a minimum input voltage of: v in(min) = v out + v f dc max Cv f + v sw where v f is the forward voltage drop of the catch diode (~0.4v) and v sw is the voltage drop of the internal switch (~0.3v at maximum load). example: i sw =0.8a and v out = 3.3v v in(min) = 3.3v + 0.4v 90% C 0.4 + 0.3v = 4v for best performance in dropout, use a 1f or larger boost capacitor. inductor selection and maximum output current a good ? rst choice for the inductor value is l = v out + v f () ? 1.8mhz f sw where v f is the voltage drop of the catch diode (~0.4v), f sw is in mhz, and l is in h. the inductors rms current rating must be greater than the maximum load current and its saturation current should be at least 30% higher. for robust operation in fault conditions (start-up or short- circuit) and high input voltage (>30v), use an 8.2h or greater inductor with a saturation rating of 2.2a, or higher. for highest ef? ciency, the series resistance (dcr) should be less than 0.1. table 2 lists several vendors and types that are suitable. www.datasheet.co.kr datasheet pdf - http://www..net/
LT3688 15 3688f applications information table 2. inductor vendors vendor part series type url murata lqh55d open www.murata.com tdk slf7045 slf10145 shielded shielded www.component.tdk.com toko dc62cb d63cb d75c d75f shielded shielded shielded open www.toko.com sumida cr54 cdrh74 cdrh6d38 cr75 open shielded shielded open www.sumida.com the optimum inductor for a given application may differ from the one indicated by this simple design guide. a larger value inductor provides a higher maximum load current, and reduces the output voltage ripple. if your load is lower than the maximum load current, then you can relax the value of the inductor and operate with higher ripple current. this allows you to use a physically smaller inductor, or one with a lower dcr resulting in higher ef? ciency. be aware that if the inductance differs from the simple rule above, then the maximum load current will depend on input voltage. in addition, low inductance may result in discontinuous mode operation, which further reduces maximum load current. discontinuous operation occurs when i out is less than i l / 2. for details of maximum output current and discontinuous mode operation, see linear technologys application note an44. finally, for duty cycles greater than 50% (v out /v in > 0.5), a minimum inductance is required to avoid sub-harmonic oscillations: l min = v out + v f () ? 1.2mhz f sw where v f is the voltage drop of the catch diode (~0.4v), f sw is in mhz, and l min is in h. the current in the inductor is a triangle wave with an average value equal to the load current. the peak switch current is equal to the output current plus half the peak-to-peak inductor ripple current. the LT3688 limits its switch cur- rent in order to protect itself and the system from overload faults. therefore, the maximum output current that the LT3688 will deliver depends on the switch current limit, the inductor value, and the input and output voltages. when the switch is off, the potential across the induc- tor is the output voltage plus the catch diode drop. this gives the peak-to-peak ripple current in the inductor i l = 1C dc () v out + v f () l?f where f is the switching frequency of the LT3688 and l is the value of the inductor. the peak inductor and switch current is i sw(pk) = i l(pk) = i out + i l 2 to maintain output regulation, this peak current must be less than the LT3688s switch current limit i lim . i lim is at least 1.25a for at low duty cycles and decreases linearly to 0.9a at dc = 0.9. the maximum output current is a function of the chosen inductor value: i out(max) = i lim C i l 2 = 1.25a ? 1C 0.3dc () C i l 2 choosing an inductor value so that the ripple current is small will allow a maximum output current near the switch current limit. one approach to choosing the inductor is to start with the simple rule given above, look at the available inductors, and choose one to meet cost or space goals. then use these equations to check that the LT3688 will be able to deliver the required output current. note again that these equations assume that the inductor current is continuous. input capacitor bypass the input of the LT3688 circuit with a ceramic capacitor of an x7r or x5r type. y5v types have poor performance over temperature and applied voltage, and should not be used. a 2.2f to 4.7f ceramic capacitor is adequate to bypass the LT3688 and will easily handle the ripple current. note that larger input capacitance is required when a lower switching frequency is used. if the input power source has high impedance, or there is signi? cant inductance due to long wires or cables, www.datasheet.co.kr datasheet pdf - http://www..net/
LT3688 16 3688f applications information additional bulk capacitance may be necessary. this can be provided with a lower performance electrolytic capacitor. step-down regulators draw current from the input supply in pulses with very fast rise and fall times. the input capacitor is required to reduce the resulting voltage ripple at the LT3688 input and to force this very high frequency switching current into a tight local loop, minimizing emi. a 2.2f capacitor is capable of this task, but only if it is placed close to the LT3688 and the catch diode (see the pcb layout section). a second precaution regarding the ceramic input capacitor concerns the maximum input voltage rating of the LT3688. a ceramic input capacitor combined with trace or cable inductance forms a high quality (under damped) tank circuit. if the LT3688 circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, possibly exceeding the LT3688s voltage rating. see linear technologys application note 88 for details. output capacitor and output ripple the output capacitor has two essential functions. along with the inductor, it ? lters the square wave generated by the LT3688 to produce the dc output. in this role it determines the output ripple, and low impedance at the switching frequency is important. the second function is to store energy in order to satisfy transient loads and stabilize the LT3688s control loop. ceramic capacitors have very low equivalent series resistance (esr) and provide the best ripple performance. a good starting value is: c out = 50 v out ?f sw where f sw is in mhz and c out is the recommended output capacitance in f. use x5r or x7r types, which will provide low output ripple and good transient response. transient performance can be improved with a high value capacitor, but a phase lead capacitor across the feedback resistor r1 may be required to get the full bene? t (see the compensation section). high performance electrolytic capacitors can be used for the output capacitor. low esr is important, so choose one that is intended for use in switching regulators. the esr should be speci? ed by the supplier and should be 0.1 or less. such a capacitor will be larger than a ceramic capacitor and will have a larger capacitance because the capacitor must be large to achieve low esr. table 3 lists several capacitor vendors. table 3. capacitor vendors vendor part series comments panasonic ceramic polymer tantalum eeef series kemet ceramic tantalum t494, t495 sanyo ceramic polymer tantalum poscap murata ceramic avx ceramic tantalum tps series taiyo yuden ceramic catch diode the catch diode conducts current only during switch-off time. average forward current in normal operation can be calculated from: i d(avg) = i out v in Cv out () v in where i out is the output load current. the only reason to consider a diode with a larger current rating than neces- sary for nominal operation is for the worst-case condition of shorted output. the diode current will then increase to the typical peak switch current limit. peak reverse voltage is equal to the regulator input voltage. use a schottky diode with a reverse voltage rating greater than the input voltage. table 4 lists several schottky diodes and their manufacturers. www.datasheet.co.kr datasheet pdf - http://www..net/
LT3688 17 3688f table 4. capacitor vendors part number v r (v) i ave (a) v f at 1a (mv) on semiconductor mbr0520l 20 0.5 mbr0540 40 0.5 620 mbrm120e 20 1 530 mbrm140 40 1 550 diodes inc. b0530w 30 0.5 b120 20 1 500 b130 30 1 500 b140hb 40 1 dfls140 40 1.1 510 ceramic capacitors ceramic capacitors are small, robust and have very low esr. however, ceramic capacitors can cause problems when used with the LT3688 due to their piezoelectric nature. when in burst mode operation, the LT3688s switching frequency depends on the load current, and at very light loads the LT3688 can excite the ceramic capacitor at audio frequencies, generating audible noise. since the LT3688 operates at a lower current limit during burst mode operation, the noise is typically very quiet. if this is unacceptable, use a high performance tantalum or electrolytic capacitor at the output. frequency compensation the LT3688 uses current mode control to regulate the output, which simpli? es loop compensation. in particular, the LT3688 does not require the esr of the output capaci- tor for stability, allowing the use of ceramic capacitors to achieve low output ripple and small circuit size. figure 3 shows an equivalent circuit for the LT3688 control loop. the error amp is a transconductance ampli? er with ? nite output impedance. the power section, consisting of the modulator, power switch and inductor, is modeled as a transconduc- tance ampli? er generating an output current proportional to the voltage at the v c node. note that the output capacitor, c1, integrates this current, and that the capacitor on the v c node (c c ) integrates the error ampli? er output current, resulting in two poles in the loop. r c provides a zero. with the recommended output capacitor, the loop cross- over occurs above the r c c c zero. this simple model works well as long as the value of the inductor is not too high and the loop crossover frequency is much lower than the switching frequency. with a larger ceramic capacitor (very low esr), crossover may be lower and a phase lead ca- pacitor (c pl ) across the feedback divider may improve the phase margin and transient response. at minimum, use a 10pf phase lead capacitor to reduce noise injection to the fb pin. if the output capacitor is different than the recom- mended capacitor, stability should be checked across all operating conditions, including load current, input voltage and temperature. the lt1375 data sheet contains a more thorough discussion of loop compensation and describes how to test the stability using a transient load. figure 4 shows the transient response when the load current is stepped from 300ma to 600ma and back to 300ma. C + 800mv v c LT3688 gnd 3688 f03 r1 out esr tantalum or electrolytic ceramic error amplifier current mode power st age fb r2 3m r c 80k c c 100pf c1 c1 g m = 1.6a/v + c pl 0.7v C + g m = 300a/v figure 3. model for the loop response figure 4. transient load response of the LT3688 front page application as the load current is stepped from 300ma to 600ma applications information v out 100mv/div i load 200ma/div 50s/div 3688 f04 www.datasheet.co.kr datasheet pdf - http://www..net/
LT3688 18 3688f low ripple burst mode operation to enhance ef? ciency at light loads, the LT3688 operates in low ripple burst mode operation that keeps the output capacitor charged to the proper voltage while minimizing the input quiescent current. during burst mode opera- tion, the LT3688 delivers single cycle bursts of current to the output capacitor followed by sleep periods where the output power is delivered to the load by the output capacitor. because the LT3688 delivers power to the output with single, low current pulses, the output ripple is kept below 25mv for a typical application. in addition, v in and bias quiescent currents are reduced to typically 65a and 155a, respectively, during the sleep time. as the load current decreases towards a no-load condition, the percentage of time that the LT3688 operates in sleep mode increases and the average input current is greatly reduced, resulting in high ef? ciency even at very low loads (see figure 5). at higher output loads the LT3688 will be running at the frequency programmed by the r t resistor, and will be operating in standard pwm mode. the transi- tion between pwm and low ripple burst mode operation is seamless, and will not disturb the output voltage. the front page application circuit will switch at full frequency at output loads higher than about 60ma. i l 0.2a/div v sw 5v/div v out 10mv/div 5s/div 3688 f05 figure 5. burst mode operation bst and bias pin considerations capacitor c3 and the internal boost schottky diodes (see the block diagram) are used to generate boost voltages that are higher than the input voltage. in most cases, a 0.22f capacitor will work well. for the best performance in dropout, use a 1f or larger capacitor. figure 6 shows v in bst sw bias v in v out 4.7f c3 gnd LT3688 (6a) for v out > 2.8v figure 6. three circuits for generating the boost voltage v in bst sw bias v in v out 4.7f c3 d2 gnd LT3688 (6b) for 2.5v < v out < 2.8v v in bst sw bias v in v out 4.7f c3 gnd LT3688 3688 f06 (6c) for v out < 2.5v; v in(max) = 30v applications information three ways to arrange the boost circuit. the bst pin must be more than 2.3v above the sw pin for best ef? ciency. for outputs of 3v and above, the standard circuit (figure 6a) is best. for outputs between 2.8v and 3v, use a 1f boost capacitor. a 2.5v output presents a special case because it is marginally adequate to support the boosted drive stage while using the internal boost diode. for reliable bst pin operation with 2.5v outputs, use a good external schottky diode (such as the on semi mbr0540), and a 1f boost capacitor (see figure 6b). for lower output voltages, the boost diode can be tied to the input (figure 6c), or to another supply greater than 2.8v. the circuit in figure 6a is more ef? cient because the bst pin current and bias pin quiescent current comes from a lower volt- www.datasheet.co.kr datasheet pdf - http://www..net/
LT3688 19 3688f age source. however, the full bene? t of the bias pin is not realized unless it is at least 3v. ensure that the maximum voltage ratings of the bst and bias pins are not exceeded. the minimum operating voltage of an LT3688 application is limited by the minimum input voltage (3.6v) and by the maximum duty cycle, as outlined in a previous section. for proper start-up, the minimum input voltage is also limited by the boost circuit. if the input voltage is ramped slowly, or the LT3688 is turned on with its en/uvlo pin when the output is already in regulation, then the boost capacitor may not be fully charged. because the boost capacitor is charged with the energy stored in the inductor, the circuit will rely on some minimum load current to get the boost circuit running properly. this minimum load will depend on input and output voltages, and on the arrangement of the boost circuit. the minimum load generally goes to zero once the circuit has started. figure 7 shows a plot of minimum load to start and to run as a function of input voltage. in many cases, the discharged output capacitor will present a load to the switcher, which will allow it to start. the plots show the worst-case situation where v in is ramping very slowly. for lower start-up voltage, the boost diode can be tied to v in ; however, this restricts the input range to one-half of the absolute maximum rating of the bst pin. at light loads, the inductor current becomes discontinuous and the effective duty cycle can be very high. this reduces the minimum input voltage to approximately 300mv above v out . at higher load currents, the inductor current is continuous and the duty cycle is limited by the maximum duty cycle of the LT3688, requiring a higher input voltage to maintain regulation. there is one particular issue to note if sequencing is used. if the bias pin is tied to v out2 , it will be low during the startup of v out1 . this will prevent the boost circuit from working on v out1 until it has risen to 90% of its programmed value, increasing the required startup volt- age. using circuit in figure 6b for v out1 will reduce the startup voltage to its normal value. an alternative is to tie bias to v out1 , if it is greater than 2.8v. soft-start and individual channel shutdown the run/ss (run/soft-start) pins are used to place the individual switching regulators in shutdown mode. they also provide a soft-start function. to shut down either figure 7. the minimum input voltage depends on output voltage, load current and boost circuit regulator, pull the run/ss pin to ground with an open- drain or collector. note that if config is tied high or low (not open), shutting down channel 1 will also shut down channel 2 because of the sequencing function (see the con? guration and sequencing section for more details). 2.5a current sources pull up on each pin. if the run/ss pin reaches ~0.2v, the channel will begin to switch if a capacitor is tied from the run/ss pin to ground, then the internal pull-up current will generate a voltage ramp on this pin. this voltage clamps the v c pin, limiting the peak switch current and therefore input current during start up. a good value for the soft-start capacitor is c out /10,000, where c out is the value of the output capacitor. the run/ss pins can be left ? oating if the soft-start feature is not used. they can also be tied together with a single capacitor providing soft-start. the internal current sources applications information load (ma) to start v out = 5v to run 1 10 100 1000 4 input voltage (v) 7 7.5 6 6.5 4.5 5 5.5 8 3688 f07a load (ma) 1 10 100 1000 3.0 input voltage (v) 6.0 6.5 5.0 5.5 3.5 4.0 4.5 7.0 3688 f07b to start to run v out = 3.3v www.datasheet.co.kr datasheet pdf - http://www..net/
LT3688 20 3688f will charge these pins to ~2v. the run/ss pins provide a soft-start function that limits peak input current to the circuit during start-up. this helps to avoid drawing more current than the input source can supply or glitching the input supply when the LT3688 is enabled. the run/ss pins do not provide an accurate delay to start or an accurately controlled ramp at the output voltage, both of which depend on the output capacitance and the load current. synchronization synchronizing the LT3688 oscillator to an external fre- quency can be done by connecting a square wave (with positive and negative pulse width > 150ns) to the sync pin. the square wave amplitude should have valleys that are below 0.4v and peaks that are above 1.3v (up to 6v). the LT3688 may be synchronized over a 350khz to 2.5mhz range. the r t resistor should be chosen to set the LT3688 switching frequency 20% below the lowest synchronization input. for example, if the synchronization signal will be 350khz and higher, r t should be chosen for 280khz. to assure reliable and safe operation, the LT3688 will only synchronize when the output voltage is above 90% of its regulated voltage. it is therefore necessary to choose a large enough inductor value to supply the required output current at the frequency set by the r t resistor (see the inductor selection section). it is also important to note that the slope compensation is set by the r t value. when the sync frequency is much higher than the one set by r t , the slope compensation will be signi? cantly reduced, which may require a larger inductor value to prevent subharmonic oscillation. shutdown and undervoltage lockout figure 8 shows how to add undervoltage lockout (uvlo) to the LT3688. typically, uvlo is used in situations where the input supply is current limited, or has a relatively high source resistance. a switching regulator draws constant power from the source, so source current increases as source voltage drops. this looks like a negative resistance load to the source and can cause the source to current limit or latch low under low source voltage conditions. uvlo prevents the regulator from operating at source voltages where the problems might occur. an internal comparator will force the part into shutdown below the minimum v in of 3.5v. this feature can be used to prevent excessive discharge of battery-operated systems. if an adjustable uvlo threshold is required, the en/uvlo pin can be used. the threshold voltage of the en/uvlo pin comparator is 1.25v. current hysteresis is added above the en threshold. this can be used to set voltage hysteresis of the uvlo using the following: r3 = v h Cv l 3.7a r4 = r3 ? 1.25v v h C 1.25v C r3 ? 0.3a example: switching should not start until the input is above 4.40v, and is to stop if the input falls below 4v. v h = 4.40v, v l = 4v r3 = 4.40v C 4v 3.7a = 107k r4 = 107k ? 1.25v 4.40v C 1.25v C 107k ? 0.3a = 43.2k 1.25v 3.7a 0.3a r3 r4c1 en/uvlo LT3688 v in run/ss v c 3688 f08 C + figure 8. undervoltage lockout applications information keep the connection from the resistor to the en/uvlo pin short and make sure the interplane or surface capacitance to switching nodes is minimized. if high resistor values are used, the en/uvlo pin should be bypassed with a 1nf capacitor to prevent coupling problems from the switch node. www.datasheet.co.kr datasheet pdf - http://www..net/
LT3688 21 3688f output voltage monitoring the LT3688 provides power supply monitoring for microprocessor-based systems. the features include power-on reset (por) and watchdog timing. a precise internal voltage reference and glitch immune precision por comparator circuits monitor the LT3688 output voltages. each channels output voltage must be above 90% of the programmed value for rst not to be asserted (refer to the timing diagram). the LT3688 will assert rst during power-up, power-down and brownout conditions. once the output voltage rises above the rst threshold, the adjustable reset timer is started and rst is released after the reset timeout period. on power-down, once the output voltage drops below rst threshold, rst is held at a logic low. the reset timer is adjustable using external capacitors. this capability helps hold the micro- processor in a stable shutdown condition. the rst pin has weak pull-up to the bias pin. the above discussion is concerned only with the dc value of the monitored supply. real supplies also have relatively high-frequency variation, from sources such as load transients, noise, and pickup. these variations should not be considered by the monitor in determining whether a supply voltage is valid or not. the variations may cause spurious outputs at rst, particularly if the supply voltage is near its trip threshold. two techniques are used to combat spurious reset without sacri? cing threshold accuracy. first, the timeout period helps prevent high-frequency variation whose frequency is above 1/ t rst from appearing at the rst output. when the voltage at fb goes below the threshold, the rst pin asserts low. when the supply recovers past the threshold, the reset timer starts (assuming it is not disabled), and rst does not go high until it ? nishes. if the supply becomes invalid any time during the timeout period, the timer resets and starts fresh when the supply next becomes valid. while the reset timeout is useful for preventing toggling of the reset output in most cases, it is not effective at preventing nuisance resets due to short glitches (due to load transients or other effects) on a valid supply. to reduce sensitivity to these short glitches, the comparator has additional anti-glitch circuitry. any transient at the input of the comparator needs to be of suf? cient magnitude and duration (t uv ) before it can change the monitor state. the combination of the reset timeout and anti-glitch circuitry prevents spurious changes in output state without sacri? cing threshold accuracy. watchdog timer the LT3688 includes an adjustable watchdog timer that monitors a ps activity. if a code execution error occurs in a p, the watchdog will detect this error and will set the wdo low. this signal can be used to interrupt a routine or to reset a p. the watchdog circuitry is triggered by negative edges on the wdi pin. the window mode restricts the wdi pins negative going pulses to appear inside a programmed time window (see the timing diagram) to prevent wdo from going low. if more than two pulses are registered in the windows fast period, the wdo is forced to go low. the wdo also goes low if no negative edge is supplied to the wdi pin in the windows slow timer period. during a code execution error, the microprocessor will output wdi pulses that would be either too fast or too slow. this condition will assert wdo and force the microprocessor to reset the program. in window mode, the wdi signal frequency is bounded by an upper and lower limit for normal operation. the wdi input frequency period should be higher than the window modes fast period and lower than the window modes slow period to keep wdo high under normal conditions. the window modes fast and slow times have a ? xed ratio of 16 between them. these times can be increased or decreased by adjusting an external capacitor on the c wdt pin. when wdo is asserted, a timer is enabled for a time equivalent to 1/8th of the watchdog window upper boundary. any wdi pulses that appear while the reset timer is running are ignored. when the timer expires, the wdo is allowed to go high again. therefore, if no input is applied to the wdi pin, then the watchdog circuitry produces a train of pulses on the wdo pin. the high time of this pulse train is equal to the watchdog window upper boundary, and low time is equal to the 1/8th of the watchdog window upper boundary. applications information www.datasheet.co.kr datasheet pdf - http://www..net/
LT3688 22 3688f if wdo is low and rst goes low, then wdo will go high. the wde pin allows the user to turn on and off the watchdog function. leaving this pin open is okay and will automatically enable the watchdog. it has an internal weak pull-down to ground. the wdi pin has an internal weak pull-up that keeps the wdi pin high. if watchdog is disabled, leaving this pin open is acceptable. con? guration and sequencing use the config pin to adjust the sequencing and the behavior of the power-on reset and watchdog timers. the table below shows all of the con? guration options. table 5. con? guration options config condition high low open channel 1 starts before channel 2 channel 1 and channel 2 start simultaneously watchdog operates only if reset 1 expires watchdog operates only if reset 1 and reset 2 expire rst1 and rst2 high only if timer 1 expires rst1 and rst2 use independent timers figure 9b. config = low applications information figure 9. startup waveforms with the three con? guration settings with the config pin tied high, v out1 will rise ? rst, as shown in figure 9a. after v out1 reaches v uv , v out2 will start increasing. in addition, the reset timer for channel 1 starts. once v out2 reaches v uv , the reset timer for channel 2 starts. once the reset timers for both channel 1 and channel 2 have expired, the watchdog will start operation. with the config pin tied low, v out1 will rise ? rst. after v out1 reaches v uv , v out2 will start increasing. the reset timer will only start if both v out1 and v out2 are above v uv , as shown in figure 9b. once the reset timer programmed by c por1 expires, both rst1 and rst2 can pull high, and the watchdog will start operation. in this mode, tie c por2 to gnd. with the config pin open, v out1 and v out2 can rise simultaneously, as shown in ? gure 9c. after v out1 reaches v uv the reset timer for channel 1 starts. once v out2 reaches v uv , the reset timer for channel 2 starts. once the reset timer for channel 1 has expired, the watchdog will start operation. figure 9a. config = high figure 9c. config = open v out1 (10v/div) v out2 (10v/div) rst1 (5v/div) rst2 (5v/div) wdo (5v/div) wdi (10v/div) 10ms/div 3688 f09a v out1 (10v/div) v out2 (10v/div) rst1 (5v/div) rst2 (5v/div) wdo (5v/div) wdi (10v/div) 10ms/div 3688 f09b v out1 (10v/div) v out2 (10v/div) rst1 (5v/div) rst2 (5v/div) wdo (5v/div) wdi (10v/div) 10ms/div 3688 f09c selecting the reset timing capacitors the reset timeout period is adjustable in order to accommodate a variety of microprocessor applications. the reset timeout period, t rst , is adjusted by connecting a capacitor, c por , between the c por pin and ground. the value of this capacitor is determined by: www.datasheet.co.kr datasheet pdf - http://www..net/
LT3688 23 3688f c por = t rst ? 200 pf ms ? ? ? ? ? ? this equation is accurate for reset timeout periods of 1ms, or greater. to program faster timeout periods, see the reset timeout period vs capacitance graph in the typical characteristics section. leaving the c por pin unconnected will generate a minimum reset timeout of approximately 65s. maximum reset timeout is limited by the largest available low leakage capacitor. the accuracy of the timeout period will be affected by capacitor leakage (the nominal charging current is 2.5a), capacitor tolerance and temperature coef? cient. a low leakage, low tempco, capacitor is recommended. selecting the watchdog timing capacitor the watchdog timeout period is adjustable and can be optimized for software execution. the watchdog window upper boundary, t wdu is adjusted by connecting a capacitor, c wdt , between the c wdt pin and ground. given a speci? ed watchdog timeout period, the capacitor is determined by: c wdt = t wdu ?50 pf ms ? ? ? ? ? ? the window lower boundary (t wdl ) and the watchdog timeout (t wdto ) have a ? xed relationship to t wdu for a given capacitor. the window lower boundary is related to t wdu by the following: t wdl = 1 16 ?t wdu the watchdog timeout is related to t wdu by the following: t wdto = 1 8 ? t wdu leaving the c wdt pin unconnected will generate a minimum watchdog window upper boundary of approximately 200s. maximum window upper boundary is limited by the largest available low leakage capacitor. the timing accuracy of the reset and watchdog signals depends on the initial accuracy and stability of the programing capacitors. use capacitors with speci? ed accuracy, leakage and voltage and temperature coef? cients. for surface mount ceramic capacitors c0g and np0 types are superior to alternatives such as x5r and x7r. applications information 5s/div v sw 10v/div i l 500ma/div 3688 f12 figure 12. the LT3688 reduces its frequency to below 70khz to protect against shorted output with 36v input shorted and reversed input protection if an inductor is chosen to prevent excessive saturation, the LT3688 will tolerate a shorted output. when operating in short-circuit condition, the LT3688 will reduce its frequency until the valley current is at a typical value of 1.2a (see figure 12). there is another situation to consider in systems where the output will be held high when the input to the LT3688 is absent. this may occur in battery charging applications or in battery backup systems where a battery or some other supply is diode ored with the LT3688s output. if the v in pin is allowed to ? oat and the en/uvlo pin is held high (either by a logic signal or because it is tied to v in ), then the LT3688s internal circuitry will pull its quiescent current through its sw pin. this is ? ne if the system can tolerate a few ma in this state. if the en/uvlo pin is grounded, the sw pin current will drop to essentially zero. however, if the v in pin is grounded while the output is held high, then parasitic diodes inside the LT3688 can pull large currents from the output through the sw pin and the v in pin. figure 13 shows a circuit that will run only when the input voltage is present and that protects against a shorted or reversed input. pcb layout for proper operation and minimum emi, care must be taken during printed circuit board layout. figure 14 shows the recommended component placement with trace, ground plane and via locations. note that large, switched currents ? ow in the LT3688s v in , da and sw pins, the catch diode (d1) and the input capacitor (c1). the loop formed by www.datasheet.co.kr datasheet pdf - http://www..net/
LT3688 24 3688f figure 14. top layer pcb layout in the LT3688 demonstration board applications information 3688 f14 these components should be as small as possible. these components, along with the inductor and output capacitor, should be placed on the same side of the circuit board. place a local, unbroken ground plane below these com- ponents. the sw and bst nodes should be as small as possible. finally, keep the fb node small so that the ground traces will shield them from the sw and bst nodes. the exposed pad on the bottom of the package must be soldered to ground so that the pad acts as a heat sink. to keep thermal resistance low, extend the ground plane as much as possible, and add thermal vias under and near the LT3688 to additional ground planes within the circuit board and on the bottom side. high temperature considerations the pcb must provide heat sinking to keep the LT3688 cool. the exposed pad on the bottom of the package must be soldered to a ground plane. this ground should be tied to large copper layers below with thermal vias; these lay- ers will spread the heat dissipated by the LT3688. placing additional vias can reduce thermal resistance further. with these steps, the thermal resistance from die (or junction) to ambient can be reduced to ja = 40c/w or less. with 100 lfpm air? ow, this resistance can fall by another 25%. further increases in air? ow will lead to lower thermal re- sistance. because of the large output current capability of the LT3688, it is possible to dissipate enough heat to raise the junction temperature beyond the absolute maximum of 125c (150c for h grade). when operating at high ambient temperatures, the maximum load current should be derated as the ambient temperature approaches 125c (150c for h grade). power dissipation within the LT3688 can be estimated by calculating the total power loss from an ef? ciency measurement and subtracting the catch diode loss. the die temperature is calculated by multiplying the LT3688 power dissipation by the thermal resistance from junction-to-ambient. thermal resistance depends on the layout of the circuit board, but values from 30c/w to 60c/w are typical. die temperature rise was measured on a 4-layer, 5cm ? 7.5cm circuit board in still air at a load current of 0.8a (f sw = 800khz). for a 12v input to 3.3v output the die temperature elevation above ambient was 14c; for 12v in to 5v out the rise was 15c and for 12v in to 5v out and 3.3v out the rise was 30c. other linear technology publications application notes 19, 35 and 44 contain more detailed descriptions and design information for buck regulators and other switching regulators. the lt1376 data sheet has a more extensive discussion of output ripple, loop compensation and stability testing. design note 318 shows how to generate a bipolar output supply using a buck regulator. v in 3688 f13 en/uvlo boost sw ltc3688 bias gnd da d4 fb v in v out + figure 13. diode d4 prevents a shorted input from discharging a backup battery tied to the output; it also protects the circuit from a reversed input. the LT3688 runs only when the input is present www.datasheet.co.kr datasheet pdf - http://www..net/
LT3688 25 3688f typical applications config v in LT3688 gnd bias en/uvlo bst1 c2 0.22f on off c1 4.7f v out1 5v 800ma v in 6v to 36v c4 22f c6 10pf c7 10pf l1 18h l2 12h r1 523k r2 100k r3 316k r4 100k c8 1nf c9 1nf p c3 0.22f sw1 da1 d2 d1 bst2 sw2 da2 fb1 run/ss1 wde wdi wdo rst1 rst2 i/o i/o reset fb2 run/ss2 c wdt c por1 c por2 rt sync c5 22f c12 1nf 3688 ta02 c10 4.7nf c11 4.7nf r5 110k c1-c5: x5r or x7r d1, d2: diodes inc. b140 f sw = 500khz v out2 3.3v 800ma 5v and 3.3v regulator with power-on reset and watchdog timers config v in LT3688 gnd bias en/uvlo bst1 c2 0.22f v out 1.8v 800ma v in 8v to 36v c4 47f c6 10pf l1 10h l2 12h r1 187k r6 475k r7 100k r2 150k r3 316k r4 100k c8 1nf c9 1nf p c3 0.22f sw1 da1 d2 d1 bst2 sw2 da2 fb1 run/ss1 wde wdi wdo rst1 rst2 i/o i/o reset fb2 run/ss2 c wdt c por1 c por2 rt sync c5 22f c7 10pf c12 1nf 3688 ta02 c10 4.7nf c11 4.7nf r5 110k c1-c5: x5r or x7r d1, d2: diodes inc. b140 f sw = 500khz v out2 3.3v 800ma c1 4.7f 3.3v and 1.8v regulator with power-on reset and watchdog timers and input under voltage lockout www.datasheet.co.kr datasheet pdf - http://www..net/
LT3688 26 3688f typical applications v in LT3688 gnd config bias en/uvlo bst1 c2 0.1f on off c1 4.7f v out1 5v 800ma v in 6v to 36v c4 10f c6 10f l1 8.2h l2 8.2h r1 523k r2 100k r3 316k r4 100k c8 1nf c9 1nf p c3 0.1f sw1 da1 d2 d1 bst2 sw2 da2 fb1 run/ss1 wde wdi wdo rst1 rst2 i/o i/o reset fb2 run/ss2 c wdt c por1 c por2 rt sync c5 22f c7 10pf c12 1nf 3688 ta04 c10 4.7nf c11 4.7nf r5 20k c1-c5: x5r or x7r d1, d2: diodes inc. b140 f sw = 2mhz: 8v < v in < 16v, t j < 85c v out2 3.3v 800ma 2mhz switching frequency, 5v and 3.3v regulator with power-on reset and watchdog timers v in LT3688 gnd bias en/uvlo bst1 c2 0.22f on off c1 4.7f v out1 1.2v 800ma v in 4v to 36v c4 100f l1 8.2h l2 15h r1 90.9k r2 182k r3 316k r4 100k c8 1nf c9 1nf p c3 0.22f sw1 da1 d2 d1 bst2 sw2 da2 fb1 run/ss1 wde wdi wdo rst1 rst2 i/o reset fb2 run/ss2 c wdt c por1 c por2 rt sync c5 22f c7 10pf c12 1nf 3688 ta05 c10 4.7nf c11 4.7nf r5 143k c1-c5: x5r or x7r d1, d2: diodes inc. b140 f sw = 400khz: v in < 25v v out2 3.3v 800ma watchdog defeat c6 10pf config 3.3v and 1.2v regulator with power-on reset timer and defeatable watchdog, timing error resets microprocessor www.datasheet.co.kr datasheet pdf - http://www..net/
LT3688 27 3688f fe24 (aa) tssop 0208 rev ? 0.09 C 0.20 (.0035 C .0079) 0o C 8o 0.25 ref recommended solder pad layout 0.50 C 0.75 (.020 C .030) 4.30 C 4.50* (.169 C .177) 134 5 6 7 8 9 10 11 12 14 13 7.70 C 7.90* (.303 C .311) 3.25 (.128) 2.74 (.108) 2021222324 19 18 17 16 15 1.20 (.047) max 0.05 C 0.15 (.002 C .006) 0.65 (.0256) bsc 0.195 C 0.30 (.0077 C .0118) typ 2 2.74 (.108) 0.45 p0.05 0.65 bsc 4.50 p0.10 6.60 p0.10 1.05 p0.10 3.25 (.128) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 24-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1771 rev ?) variation aa package description information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. uf package 24-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1697) 4.00 0.10 (4 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wggd-x)to be approved 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 2423 1 2 bottom viewexposed pad 2.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 C 0.05 (uf24) qfn 0105 recommended solder pad pitch and dimensions 0.70 0.05 0.25 0.05 0.50 bsc 2.45 0.05 (4 sides) 3.10 0.05 4.50 0.05 package outline pin 1 notch r = 0.20 typ or 0.35 45 chamfer www.datasheet.co.kr datasheet pdf - http://www..net/
LT3688 28 3688f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com linear technology corporation 2011 lt 0111 ? printed in usa related parts part number description comments lt3640 35v, 55v max, dual (1.3a, 1.1a), 2.5mhz high ef? ciency step- down dc/dc converter with por reset and watchdog timer v in min = 4v, v in max = 35v, transient to 55v, v out(min) = 0.6v, i q = <290a, i sd = <1a, 4mm 5mm qfn-28 tssop-28e package lt3689/lt3689C5 36v, 60v transient protection, 800ma, 2.2mhz high ef? ciency micropower step-down dc/dc converter with por reset and watchdog timer v in min = 3.6v, v in max = 36v, transient to 60v, v out(min) = 0.8v, i q = 75a, i sd = <1a, 3mm 3mm qfn-16 package lt3686 37v, 55vmax, 1.2a, 2.5mhz high ef? ciency step-down dc/dc converter v in min = 3.6v, v in max = 37v, transient to 55v, v out(min) = 1.21v, i q = 1.1ma, i sd = <1a, 3mm 3mm dfn-10 package lt3682 36v, 60vmax, 1a, 2.2mhz high ef? ciency micropower step- down dc/dc converter v in min = 3.6v, v in max = 36v, v out(min) = 0.8v, i q = 75a, i sd = <1a, 3mm 3mm dfn-12 package lt3971 38v, 1.2a (i out ), 2mhz, high ef? ciency step-down dc/dc converter with only 2.8ua of quiescent current v in min = 4.2v, v in max = 38v, v out(min) = 1.2v, i q = 2.8a, i sd = <1a, 3mm 3mm dfn-10, msop-10e package lt3991 55v, 1.2a (i out ), 2mhz, high ef? ciency step-down dc/dc converter with only 2.8ua of quiescent current v in min = 4.2v, v in max = 55v, v out(min) = 1.2v, i q = 2.8a, i sd = <1a, 3mm 3mm dfn-10, msop-10e package lt3970 40v, 350ma (i out ), 2mhz, high ef? ciency step-down dc/dc converter with only 2.5ua of quiescent current v in min = 4.2v, v in max = 40v, v out(min) = 1.2v, i q = 2.5a, i sd = <1a, 2mm 3mm dfn-10, msop-10e package lt3990 60v, 350ma (i out ), 2mhz, high ef? ciency step-down dc/dc converter with only 2.5ua of quiescent current v in min = 4.2v, v in max = 60v, v out(min) = 1.2v, i q = 2.5a, i sd = <1a, 3mm 3mm dfn-10, msop-16e package typical application config v in LT3688 gnd bias en/uvlo bst1 c2 0.22f on off c1 4.7f v out1 5v 800ma v in 6v to 36v c4 22f c6 10pf c7 10pf l1 18h l2 12h r1 523k r2 100k r3 340k r4 100k c8 1nf c9 1nf p c3 0.22f sw1 da1 d2 d1 bst2 sw2 da2 fb1 run/ss1 wde wdi wdo rst1 rst2 i/o i/o reset fb2 run/ss2 c wdt c por1 c por2 rt sync c5 22f c12 1nf 3688 ta06 c10 4.7nf c11 4.7nf r5 49.9k c1-c5: x5r or x7r d1, d2: dfls140 f sw = 1mhz: 7v < v in < 21v v out2 3.3v 800ma 1mhz 5v and 3.3v regulator with power-on reset and watchdog timers www.datasheet.co.kr datasheet pdf - http://www..net/

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